A) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device manufactured, and more particularly to a method of manufacturing a semiconductor device having shallow trench isolation (STI)and a semiconductor device manufactured thereby.
B) Description of the Related Art
Local oxidation of silicon (LOCOS) has been used as isolation of a semiconductor device.
According to LOCOS techniques, after a silicon oxide layer is formed on a silicon substrate as a buffer layer, a silicon nitride layer is formed. After the silicon nitride layer serving as an oxidation preventive mask layer is patterned, the surface of the silicon substrate is thermally oxidized.
Oxidizing species such as oxygen and moisture enter the buffer silicon oxide layer when the silicon substrate is thermally oxidized. These oxidizing species oxidize also the silicon substrate surface under the edge of the silicon nitride layer through the buffer oxide layer and silicon oxide regions called birds' beaks are formed. Although the bird's beak region is outside the isolation region, this bird's beak region cannot be used as an active region for forming electronic elements so that the area of the active region is reduced.
A silicon nitride layer having apertures of various sizes is formed on a silicon substrate and the substrate surface is thermally oxidized. A silicon oxide layer formed on the silicon substrate surface in a small size aperture is thinner than a silicon oxide layer formed on the silicon substrate surface in a large size aperture. This phenomenon is called thinning.
As a semiconductor device becomes miniaturized, a ratio of an area not used as the electronic element forming region to a total area of a semiconductor substrate increases. Namely, a ratio of narrowing the electronic element forming region increases, hindering high integration of a semiconductor device.
Trench isolation (TI) techniques are known as isolation region forming techniques. According to TI techniques, a trench is formed in the surface layer of a semiconductor substrate and insulator or polysilicon is filled or buried in the trench. This method has been used for forming a bipolar transistor LSI which requires deep isolation regions.
Trench isolation is being applied to a MOS transistor LSI in order to eliminate both bird's beak and thinning. MOS transistor LSI's do not require deep isolation regions like bipolar transistor LSI's and can use relatively shallow isolation regions having a depth of about 0.1 to 1.0 μm, which is called shallow trench isolation (STI).
According to a proposed STI forming method, after a trench is formed, a liner layer made of a silicon oxide layer and a silicon nitride layer is formed and a filling or burying silicon oxide layer is formed on the liner layer.
Reference is made to Japanese Patent Laid-open publication Nos. HEI-11-297811 and 2000-31261, U.S. Pat. No. 5,447,884, which is incorporated herein by reference, and Japanese Patent Laid-open Publication Nos. HEI-10-56058 and 2003-273206 corresponding to U.S. patent application Ser. No. 10/283,128 filed on Oct. 30, 2002, which is incorporated herein by reference.
STI is fitted for miniaturization, but there may arise other problems unique to STI. Novel techniques for solving problems unique to STI are being desired.